1. Field of the Invention
The present invention relates to an operational amplifier and related method of enhancing slew rate, and more particularly, to an operational amplifier and related method that reallocates current intensities of an amplification stage bias current and an output stage drive current to increase drive capability of the amplification stage circuit.
2. Description of the Prior Art
An operational amplifier is a widely used element for realizing a variety of circuit functions. Taking driving circuits of a liquid crystal display (LCD) as an example, the operational amplifier can be used as an output buffer, which charges or discharges loads, i.e. liquid crystals, according to analog signals outputted by a front stage digital to analog converter (DAC), for driving corresponding pixel units on the LCD. However, with increases in size and resolution of the LCD, data quantity processed by the driving circuits is also increasing significantly, so that response speed of the operational amplifier, also called slew rate, has to be enhanced as well.
In a conventional driver chip, the operational amplifier generally has a two-stage structure, which includes a first stage amplification circuit (amplification stage) and a second stage output circuit (output stage). The first stage amplification circuit is utilized for increasing current or voltage gain of the operational amplifier, while the second stage output circuit is utilized for driving capacitive or resistive loads connected to the operational amplifier. In addition, since the operational amplifier may suffer loop instability problems, Miller compensation capacitors are commonly used to perform frequency compensation for improving loop stability.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional operational amplifier 100. For brevity, the operational amplifier 100 is an operational amplifier with a simplest circuit structure, and merely has an N-type input differential pair. The operational amplifier 100 mainly includes an amplification stage circuit 110, an output stage circuit 120, a first bias current source 115 and a second bias current source 125. The amplification stage circuit 110 is formed by transistors MP1, MP2, MN1 and MN2. The output stage circuit 120 is formed by a transistor MPO that has a common emitter configuration. The first bias current source 115 and the second bias current source 125 are utilized for providing fixed static currents (or driving currents) IT1 and IT2 for the amplification stage circuit 110 and the output stage circuit 120, respectively. Furthermore, an output terminal Vout of the output stage circuit 120 is further coupled to an input terminal AVN of the amplification stage circuit 110 for forming an output buffer with unit gain and negative feedback. In addition, a compensation capacitor CM is coupled between an output terminal of the amplification stage circuit 110, i.e. a drain of the transistor MN2, and the output terminal Vout of the output stage circuit 120, and is utilized for performing pole-splitting for output signals of the amplification stage circuit 110 and the output stage circuit 120, so as to enhance loop stability. Detailed operation of the operational amplifier 100 is well-known by those skilled in the art, and not narrated herein.
Specifically, the response speed of the operational amplifier 100 is decided by the bias currents of the amplification stage circuit and the output stage circuit. However, in order to drive external loads of the operational amplifier 100, the output stage drive current is generally greater than the amplification stage bias current. In this case, when the operational amplifier drives a heavy load, the response speed is often restricted by the bias current of the amplification stage circuit.
Please refer to FIG. 2. FIG. 2 illustrates an internal current path of the operational amplifier 100 when an input signal of the operational amplifier 100 is converted from low to high. Since a voltage level of the input terminal AVP is raised immediately when the input signal of the operational amplifier 100 is converted, the transistors MN1, MP1 and MP2 are then switched off, so that the first bias current source 115 can only draw the bias current IT1 from the compensation capacitor CM through the transistor MN2 for pulling up the voltage level of the output terminal Vout. The above current path is shown as PATH_1 in FIG. 2. On the other hand, please refer to FIG. 3, which illustrates an internal current path of the operational amplifier 100 when the input signal of the operational amplifier 100 is converted from high to low. Since the voltage level of the input terminal AVP is dropped immediately when the input signal is converted, the transistor MN2 is then switched off, so that the bias current IT1 is drawn entirely through the transistor MN1. Additionally, since the transistors MP1 and MP2 have a current mirror structure, a current with intensity the same as the bias current IT1 also simultaneously flows to the ground through the compensation capacitor CM, so as to pull down the voltage level of the output terminal Vout. The above current path is shown as PATH_2 in FIG. 3.
Thus, it can be seen that the response speed of the operational amplifier 100 depends on how fast the bias current IT1 of the amplification stage circuit charges or discharges the compensation capacitor CM, and can be expressed by the following slew rate equation:
      S    ⁢                  ⁢    R    =                    I                  T          ⁢                                          ⁢          1                            C        M              =                            Δ          ⁢                                          ⁢          V                t            .      Thus, if the amplification stage bias current increases, the compensation capacitor can be charged or discharged much faster, so that the response speed of the operational amplifier 100 can be enhanced.
In the prior art, the internal slew rate of the operational amplifier is generally enhanced by increasing the bias current IT1 of the amplification stage circuit. However, this not only increases circuit area, e.g. by increasing layout area of the bias transistors, but also causes additional power consumption of the operational amplifier. Thus, an import issue for circuit designers in this art is how to increase the slew rate of the operational amplifier without increasing power consumption.